nam a22 7a 4500 2528 2528 20180320164132.0 180320b xxu||||| |||| 00| 0 eng d 9783319025469 eng 005.71 EDU EDUARDO AUGUSTO BEZERRA SYNTHESIZABLE VHDL DESIGN FOR FPGAs SWITZERLAND SPRINGER 2014 157 DJONES VINICIUS LETTNIN BK 0 0 0 0 ECE IITTP IITTP GEN 2018-03-20 Shankar's Book 8158.05 IN20695/17-18 1 005.71 EDU 04257 2025-09-25 00:00:00 2025-09-25 9597.71 2018-01-02 BK