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  <titleInfo>
    <title>Digital Design</title>
    <subTitle>An Embedded Systems Approach Using Verilog</subTitle>
  </titleInfo>
  <name type="personal">
    <namePart>Ashenden, Peter J.</namePart>
    <role>
      <roleTerm authority="marcrelator" type="text">creator</roleTerm>
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  <typeOfResource>text</typeOfResource>
  <originInfo>
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    <publisher>Elsevier</publisher>
    <dateIssued>©2018</dateIssued>
    <issuance>monographic</issuance>
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  <language>
    <languageTerm authority="iso639-2b" type="code">eng</languageTerm>
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    <extent>xx, 557p.</extent>
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  <subject>
    <topic>System Design</topic>
  </subject>
  <subject>
    <topic>Embedded Computer Systems</topic>
  </subject>
  <subject>
    <topic>VHDL (Computer hardware description language)</topic>
  </subject>
  <classification authority="ddc">621.3916 AshD</classification>
  <identifier type="isbn">9788190935630</identifier>
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    <recordCreationDate encoding="marc">210915</recordCreationDate>
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